1. Field of the Invention
The present invention relates to a solid-state imaging device and an electronic device including the solid-state imaging device.
2. Description of the Related Art
CMOS (Complementary Metal-Oxide-Semiconductor) solid-state imaging devices (CMOS image sensors) are solid-state imaging devices particularly attracting attention in recent years. Such a CMOS solid-state imaging device includes an imaging region having many pixels arranged in a two-dimensional matrix; and a peripheral circuit provided around the imaging region. In the imaging region, each of the pixels has a floating diffusion (FD) layer of converting charges from a photoelectric conversion portion (photodiode: PD) into voltage signals; a transfer transistor of transferring the charges from the photodiode to the floating diffusion portion; a reset transistor of resetting the charges in the floating diffusion portion; and an amplifying transistor of outputting a potential of the floating diffusion portion as a signal level.
A configuration of a CMOS solid-state imaging device of the related art (a relation between an imaging region and a peripheral circuit) will be specifically described with reference to FIG. 1. The solid-state imaging device 101 of the related art includes, on a common semiconductor substrate, an imaging region 102 having many pixels 101a each formed by a photodiode and several transistors and arranged in a two-dimensional matrix; and a peripheral circuit of controlling the transistors in the imaging region 102 to detect an output signal from each of the pixels 101a. In this example, the peripheral circuit has a vertical driving circuit 103, a column signal processing circuit 104; a horizontal driving circuit 105; a horizontal signal line 106; an output circuit 107; and a control circuit 108.
In the imaging region 102 of the solid-state imaging device 101, row control lines are each wired in a transverse direction (horizontal direction) of the figure for each row of the plurality of pixels 101a arranged in a two-dimensional matrix, and vertical signal lines 109 are each wired in a longitudinal direction (vertical direction) of the figure for each line of the pixels. In the imaging region, light from outside is collected in the photodiode to cause photoelectric conversion, so that signal charges are generated corresponding to an amount of light. When a control pulse enters a read gate of a transfer transistor provided in each of the pixels, the signal charges are transferred to a floating diffusion portion from the photodiode. A potential of the floating diffusion portion is changed by transference of the charges. The floating diffusion portion is connected to a gate of an amplifying transistor, so that current based on the change in potential of the floating diffusion portion is transmitted to the peripheral circuit through a vertical signal line.
In the solid-state imaging device 101 having such a configuration, the pixels 101a in the imaging region 102 are each sequentially selected and scanned row by row by the vertical driving circuit 103 formed by a shift resistor and the like. Accordingly, a necessary control pulse is supplied to each of the pixels in the selected row through the aforementioned row control line. A signal output from each of the pixels in the selected row is supplied to the column signal processing circuit 104 through the vertical signal line 109. The column signal processing circuit 104 receives the signals output from one row of pixels 101a according to columns. The signals are subjected to processing such as CDS (Correlated Double Sampling) to remove fixed pattern noise inherent to the pixels 101a or signal amplification. The processed signals are output as pixel signals from each of the column signal processing circuits 104. Specifically, the column signal processing circuits 104 are each sequentially selected by the horizontal driving circuit 105 formed by a shift resister, for example, so that the signals are sequentially output as horizontal scanning pulses φH1 to φHn. In the output circuit 107, the signals sequentially supplied from each of the column signal processing circuits 104 through the horizontal signal line 106 are subjected to various types of processing. Specific examples of the signal processing in the output circuit 107 include buffering. Examples of processing prior to buffering include black level adjustment, correction of variation between the lines, signal amplification, and color relation processing. The control circuit 108 receives data to instruct an operation mode or the like of the solid-state imaging device 101 from outside; and outputs data including information of the solid-state imaging device 101 of the related art. The control circuit also generates a clock signal, a control signal, and the like as criteria for operation of the vertical driving circuit 103, the column signal processing circuits 104, the horizontal driving circuit 105, and the like based on a vertical synchronizing signal, a horizontal synchronizing signal, a master clock, and the like, and supplies the signals to the vertical driving circuit 103, the column signal processing circuits 104, the horizontal driving circuit 105, and the like.
Here, the pixel 101a may be configured to have a so-called three-transistor circuit shown in FIG. 2, for example. In this circuit configuration, a cathode (n-type region) of a photodiode is connected to a gate of an amplifying transistor Tr3 through a transfer transistor Tr1. A node electrically linked to the gate of the amplifying transistor Tr3 is called a floating diffusion portion. The transfer transistor Tr1 is connected to a transfer line 111 between the photodiode and the floating diffusion portion; is turned on by supplying a transfer pulse φTRG to a gate of the transfer transistor Tr1 through the transfer line 111; and transfers signal charges photoelectrically converted in the photodiode to the floating diffusion portion.
A reset transistor Tr2 has a drain connected to a pixel power supply Vdd1 and a source connected to the floating diffusion portion. The reset transistor Tr2 is turned on by supplying a reset pulse φRST to a gate of the reset transistor Tr2 through a reset line 112; and discharges charges in the floating diffusion portion to the pixel power supply Vdd1 to reset the floating diffusion portion prior to transfer of the signal charges to the floating diffusion portion from the photodiode. The amplifying resistor Tr3 has a gate connected to the floating diffusion portion, a drain connected to a pixel power supply Vdd2, and a source connected to a vertical signal line 113. The amplifying transistor Tr3 outputs a potential of the floating diffusion portion after being reset by the reset transistor Tr2 to the vertical signal line as a reset level; and outputs a potential of the floating diffusion portion to the vertical signal line 113 as a signal level after the transfer transistor Tr1 transfers the signal charges. The pixel power supply Vdd1 is switched between a high level and a lower level by driving the pixel, so that the drain of the amplifying transistor Tr3 is changed.
Alternatively, the pixel 101a may be configured to have a so-called four-transistor circuit shown in FIG. 3, for example. This circuit configuration has four transistors Tr1 to Tr4 in addition to a photoelectric conversion element, for example a photodiode. Here, the transistors Tr1 to Tr4 are formed as N-channel MOS transistors, for example. The photodiode photoelectrically converts received light into an amount of optical charges (electrons in this case) corresponding to an amount of the light. A cathode (n-type region) of the photodiode is connected to a gate of the amplifying transistor Tr3 through the transfer transistor Tr1. A node electrically linked to the gate of the amplifying transistor Tr3 forms a floating diffusion portion.
Wirings in a transverse direction, specifically, a transfer line 114, a reset line 115, and a selection line 116 are common for the pixels in an identical row and controlled by the vertical driving circuit. However, a p well wiring 117 to fix a p well potential of the pixel 101a is fixed to a ground potential. In this configuration, the transfer transistor Tr1 is connected to the transfer line 114 between the cathode of the photodiode and the floating diffusion portion; is turned on by supplying a transfer pulse φTRG to a gate of the transfer transistor Tr1 through the transfer line 111; and transfers the optical charges photoelectrically converted in the photodiode to the floating diffusion portion.
The reset transistor Tr2 has a drain connected to a pixel power supply Vdd and a source connected to the floating diffusion portion; is turned on by supplying a reset pulse φRST to a gate of the reset transistor Tr2 through the reset line 115; and discharges charges in the floating diffusion portion to the pixel power supply Vdd to reset the floating diffusion portion prior to transfer of the signal charges to the floating diffusion portion from the photodiode. The amplifying transistor Tr3 has a gate connected to the floating diffusion portion and a drain connected to the pixel power supply Vdd; outputs a potential of the floating diffusion portion after being reset by the reset transistor Tr2 as a reset level; and outputs a potential of the floating diffusion portion as a signal level after the transfer transistor Tr1 transfers the signal charges.
The selection transistor Tr4 has a drain connected to a source of the amplifying transistor Tr3 and a source connected to a vertical signal line 118, for example; is turned on by supplying a reset pulse φSEL to a gate of the selection transistor Tr4 through the selection line 116; and relays a signal output from the amplifying transistor Tr3 to the vertical signal line 118, with the pixel 101a in a selected state.
A photodiode and each transistor in a pixel are typically formed on a common semiconductor substrate; however, each transistor has different important properties.
For example, properties important for a transistor in a peripheral circuit (peripheral transistor; peripheral Tr) are high-speed operation and low power consumption. On the other hand, properties important for a transistor in an imaging region (pixel transistor; pixel Tr), particularly a transfer transistor, are low noise and uniformity (small difference between transistors). Examples of the pixel transistor include an amplifying transistor (AMP transistor), a selection transistor (SEL transistor), and a reset transistor (RST transistor) as described above, in addition to the transfer transistor.
However, in the manufacture of a solid-state imaging device, it is preferable to form pixel transistors and peripheral transistors at the same time to reduce the number of processes, because elements are often formed by many processes.
Examples of such processes for forming a transistor include formation of a well, channel implantation, formation of a gate oxide film and a gate, formation of a side wall, formation of an LDD (Lightly Doped Drain) structure, formation of a source and a drain by implantation, and silicidation. The number of processes, cost, and lead time may be reduced by commonly using these processes for forming peripheral transistors and pixel transistors.
The following methods are proposed for formation of different transistor elements having different demanded properties by use of common processes (e.g. Japanese Unexamined Patent Application Publication No. 2006-24786).
In a first method, high-energy implantation is used for forming a photodiode with a large amount of saturation charges in formation of a well region in an imaging region, and different implantation is used in formation of a well region of a transistor in a peripheral circuit. In a second method, metal silicides (such as TiSi2, CoSi2, NiSi, and PtSi) are used for a transistor in a peripheral circuit demanded to be driven at high speed to reduce various resistances (resistance of a gate electrode, sheet resistance and contact resistance of a source and a drain of a transistor), while silicidation is avoided for a pixel transistor to prevent a high-melting metal generating excess electrons from being included in a photodiode in order to suppress generation of white spots in image data. Formation of different transistors involving silicidation may be performed by a method of forming a high-melting metal block film made of SiN or the like in an imaging region, for example.
It is preferable to perform such first and second methods and furthermore commonly perform the remaining processes (such as channel implantation, formation of a gate oxide film, formation of a gate electrode, and extension implantation) for forming different transistors.
However, in recent years, electronic devices (applications such as portable telephones and video cameras) having a solid-state imaging device has been increasingly demanded to be reduced in size and weight. Accordingly, not only does a lens tend to be reduced in size, but also an optical size in a solid-state imaging device (area occupied by one pixel; pixel size) tends to be reduced. Such a tendency to reduce an optical size is strongly desired to provide image data with increased fineness. Further, specifications (such as materials and dimensions) of elements are often limited by the level of manufacturing technology in a particular era (so-called process generation). Therefore, it may be difficult to modify conditions for forming peripheral transistors even when an optical size is reduced. That is, it may be necessary to reduce an optical size while using common formation processes for peripheral transistors and pixel transistors and not modifying formation conditions for peripheral transistors.
Accordingly, in the manufacture of a small and lightweight solid-state imaging device under the present circumstances, it may be difficult to modify common conditions for pixel transistors and peripheral transistors, while implantation conditions may have to be controlled in forming a photodiode to reduce an optical size. Under such circumstances, it may be difficult to provide pixel transistors with properties basically demanded for the transistors, and some drawbacks may be observed particularly in a floating diffusion portion. Specifically, since a large amount of impurities (ions) are implanted into a source and a drain of a transistor to form a diffusion layer, a strong electric field is formed between a P well and the source and drain, so that a volume of the floating diffusion portion is increased and conversion efficiency is decreased.
Further, since electric field concentration is increased near an edge of a transfer transistor gate (TRG), excess electrons flow into the floating diffusion portion due to a crystal defect or the like, so that white spots in the dark are generated in image data. A photoelectric conversion portion is difficult to be driven at low voltage due to an S/N (signal/noise) ratio and the like. When such electric field concentration occurs, white spots may increasingly be generated. White spots generated in this manner differ from general white spots caused by a defect in a photodiode in terms of dependence on temperature and accumulation time, and the presence or absence of the white spots and the degree of the white spots vary between pixels. Therefore, it is difficult to appropriately correct the white spots. Electric field intensity on a TRG edge is simulated, and it is observed that the electric field intensity on the TRG edge is increased by 15% when a pixel area is reduced by 35% without modifying existing process conditions. White spots are increasingly generated in accordance with such an increase in electric field intensity.
Further, as the pixel cell area is miniaturized, a so-called pixel-sharing structure may be adopted, in which parts of the transistors in each pixel are shared by a plurality of pixels to maintain the light reception area of a photoelectric conversion portion. In the case of the pixel-sharing construction, often the floating diffusion portion FD is divided, and in addition to parasitic capacitance due to the diffusion region of respective divided floating diffusion portions FD, the wiring capacitance of a metal wiring connecting the divided floating diffusion portions FD is added, and the conversion efficiency decreases as compared with the case that the pixel-sharing construction is not adopted.
Meanwhile, the electron number that indicates the signal charge is determined by the amount of charge processed in the imaging portion and the floating diffusion portion FD forming the charge accumulation portion. This electron (signal charge) is output to the vertical signal line as a voltage change by means of the source follower operation of an amplifying transistor. In this case, it is preferable to decrease the parasitic capacitance of the floating diffusion portion FD to enhance the conversion efficiency.
Various methods for producing solid-state imaging elements are proposed; for example, Japanese Unexamined Patent Application Publication No. 2004-165479 and Japanese Unexamined Patent Application Publication No. 2005-268812 disclose methods for decreasing the parasitic capacitance.